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Systolic arrays within heterogeneous computing platforms allow for substantial performance gains in numerical methods, combinatorial problem solving, as well as in image, signal, speech, and text processing. Systolic arrays use accelerates tensor computations by reducing memory traffic and avoiding the transfer of intermediate data through external subsystems. However, available open-source implementations are limited in scope and lack the ability to be reconfigured. In this work, reconfigurable systolic array architecture is proposed based on two fundamental modes: with static sums (Output Stationary) and static weights (Weight Stationary). It has been established that the preferable configuration depends on the target workload. In operations requiring high computational speed it is advisable to use mode with static sums. In that case, the execution cycles’ number is reduced 27-fold in average. When energy efficiency and reduction in number of memory requests are in priority, mode with static weights is more advantageous. Consequently, in convolutional tasks, memory access requirements are lowered by approximately 1.5 times. The research outcomes may find application in the design of systems requiring flexible and resource-efficient implementation of tensor operations customized according to specific operating conditions.

Key words: systolic array, static sums, static weights, Output Stationary, Weight Stationary, reconfigurable structure, quantization, neural networks
Published in: INFORMATION-COMMUNICATION TECHNOLOGIES
Bibliography link: Gurzhov N. A., Pereverzev A. L., Primakov E. V., Silantiev A. M., Solodovnikov A. P., Chusov S. A., Yakunin A. N. Architecture of reconfigurable systolic array for neural network booster. Izv. vuzov. Elektronika = Proc. Univ. Electronics. 2026;31(2):225–239. (In Russ.). https://doi.org/10.24151/1561-5405-2026-31-2-225-239.

Nikita A. Gurzhov
National Research University of Electronic Technology, Russia, 124498, Moscow, Zelenograd, Shokin sq., 1

Alexey L. Pereverzev
National Research University of Electronic Technology, Russia, 124498, Moscow, Zelenograd, Shokin sq., 1

Evgeny V. Primakov
National Research University of Electronic Technology, Russia, 124498, Moscow, Zelenograd, Shokin sq., 1

Aleksander M. Silantiev
National Research University of Electronic Technology, Russia, 124498, Moscow, Zelenograd, Shokin sq., 1

Andrey P. Solodovnikov
National Research University of Electronic Technology, Russia, 124498, Moscow, Zelenograd, Shokin sq., 1

Sergey A. Chusov
National Research University of Electronic Technology, Russia, 124498, Moscow, Zelenograd, Shokin sq., 1

Aleksey N. Yakunin
National Research University of Electronic Technology, Russia, 124498, Moscow, Zelenograd, Shokin sq., 1

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Publication type: Scientific article
Source lang: Russian
DOI: 10.24151/1561-5405-2026-31-2-225-239
RISC id: QUZQJF

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